1. Field of Invention
Embodiments of the invention relate generally to memory systems, and more particularly, to access of memory.
2. Description of Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art.
Electronic systems typically include one or more memory components, which may be accessed by various other components, such as other devices or applications in the electronic system. A memory component may be, for example, any data structure including a sequence or group of data elements. In some embodiments, a memory component may be a memory array, such as a dynamic random access memory (DRAM) array. A memory component may also be a bank or banks which make up a memory array. For example, a controller in the electronic system may access data in memory components, such as a memory array, to obtain data for processing. A “controller” may refer to any component, such as a processor, capable of substantially controlling access to the memory component. For example, the controller may open or close pages in the memory component, and may receive and grant requests from other components of the system to access the memory component. The controller may be a silicon-on chip (SOC), which may be external to a memory device or memory system containing a memory component. Further, in some embodiments, the controller may also be an internal processor embedded on or packaged with the memory device containing the memory component. Further, other components of the electronic system may also store data in the memory components.
Generally, more than one component of the electronic system may request access to a memory component, which may have multiple banks, each further including a number of pages. As used herein, a “page” refers to a row, or any other sequence or group of data elements organized in a memory. However, in a typical memory component, each bank may have only one page open at a time. For example, while a first component in the system may have access to a row in a bank, a second component may have to wait for the system to close the open row before a row requested by the second component is opened. Thus, the number of transactions between system components and the memory components may be limited by the access patterns of all the components requesting access to the memory.
In some systems, rows are configured to be left open once they are requested, and a component targeting the open row would not have to wait for the row to be opened. This “open page policy” may be advantageous for systems where requests for certain rows in a memory component are relatively predictable (e.g., a frequently requested row). In other systems, rows may be configured to close once a transaction is completed. This “closed page policy” may be implemented in systems where page access patterns are more random. However, the open page policy may require more power to operate, and the closed page policy may require more time to process each access request. Furthermore, in typical electronic systems, once a system is configured to have an open page policy or a closed page policy, the policy is set. The limitations of opening only one page at a time, and the set policy on page access in a memory bank may limit the efficiency of transactions in an electronic system